FIG. 1A is an example circuit block diagram of a typical delay path in a digital circuit. The delay path is widely applied to microprocessors and other digital circuits. The flip-flop 102 is coupled to a flip-flop 106 through combination logic 104. In the flip-flops 102, 106, D is the data input end, Q is the data output end, and CK is the clock signal receiving end. The flip-flops 102, 106 are controlled by the clock signal. FIG. 1B is an example clock diagram of the operating delay of FIG. 1A. Referring to FIG. 1A and FIG. 1B, during the first positive triggering of the clock signal, the flip-flop 102 releases data to the combinational logic unit 104. At this time, before the data is exactly displayed by the flip-flop 102, a CK-Q (clock versus output value) delay time interval 114 occurs. Once the data is generated by the flip-flop 102, it is input into the flip-flop 106 though the combinational logic 104, and the time interval for transmitting the data in the combinational logic unit 104 is the transmitting time interval 116. Moreover, the set-up time interval 118 is related to the state setting of the flip-flop 106. Therefore, the delay (critical timing) 112 can be considered to be the sum of the CK-Q time interval 114, the transmitting time interval 116, and the set-up time interval 118.
In conventional structures using multiplexers in addition to the latches either for multiple inputs or multiple latches, the multiplexer delay worsens the CK-Q time 114 or the set-up time 118, depending on where the multiplexer is placed. As a result, they have longer delay time 112. Also, even if a conventional structure does not use a multiplexer, reducing the delay time 112 is still an important issue. Accordingly, new structures and methods for flip-flops are desired that can reduce the overall delay 112.